The present invention relates to a verification method for generation of a semiconductor device pattern with which pattern formation and surface planarization are achieved with high precision according to the process conditions of a semiconductor device.
In recent years, semiconductor devices, especially large scale integration (LSI) semiconductor devices, have been key devices that are indispensable for electric machines. Accordingly, the degree of miniaturization and the degree of integration have been advancing, and the necessity for finer and more complicated pattern formation has been increasing. In such circumstances, restrictions to the process conditions that achieve pattern formation as designed have been increasing.
For example, in a wiring pattern formation process, after a conductive film, such as a polysilicon layer, an aluminum layer, a metal silicide layer, or the like, is formed, a desired mask pattern is formed by photolithography, and thereafter, etching is performed using the mask pattern, whereby the wiring pattern is formed.
In the etching process, part of the conductive film which is exposed through the mask pattern is selectively removed. At this step, even if the conditions of the etching process are optimized, the etching rate varies due to a variation in the density of the mask pattern (pattern area ratio) or the perimeter length of the mask pattern. Accordingly, the etching accuracy changes according to the pattern area ratio or the pattern pitch. As a result, the etching accuracy deteriorates when the mask pattern area is excessively large or excessively small.
Such problems may also occur in the formation of a diffusion layer. In the case where the ion implantation region is too small for the formation of the diffusion layer, concentration of ions occurs in the region so that a desired diffusion profile is not obtained.
CMP (Chemical Mechanical Polishing) method has been proposed for planarization of the substrate surface. In this method, mechanical polishing and chemical polishing are concomitantly performed on an insulating film which has been formed over a substrate surface by a coating method, a CVD (Chemical Vapor Deposition) method, or the like, whereby a flat substrate surface (the surface of the insulating film) is achieved. However, in the case where the pattern density of an underlying wiring layer formed of aluminum wirings, for example, is small, i.e., in the case where a region larger than a predetermined area includes no wiring pattern, the insulating film cannot have a flat surface even if the insulating film on the wiring layer is formed thicker. As a result, a concavity is formed in the region including no wiring pattern even when CMP is performed on the insulating film, and even in the following steps, the concavity still has the concave shape.
In such a case where the layout pattern of a certain layer in a semiconductor device is not uniform, sufficient pattern accuracy is not obtained in the layer, and in addition, the pattern accuracy is affected in the upper layers. As a result, the process accuracy is not sufficiently attained.
In order to solve the above problems, it is necessary to efficiently verify and adjust the area ratio in the certain layer which is obtained based on the process conditions (the pattern area ratio in each of a plurality of check windows (data windows) that cover the certain layer (hereinafter, referred to as “pattern occupancy ratio” for distinguishing from the pattern area ratio which indicates the area ratio over the entire chip area).
As a pattern placement method for achieving a desired value (target value) of the pattern area ratio or pattern occupancy ratio, a method for placing a dummy pattern in an unoccupied region of each check window (a region where none of various patterns, such as a wiring pattern, a device patter, etc., is formed) while changing the pitch and shape of the dummy pattern such that, for example, the pattern occupancy ratio satisfies a target value, has been proposed (for example, Japanese Unexamined Patent Publication No. 2002-9161).
Calculation method and pattern placement method for determining a dummy pattern to be placed in an unoccupied region have also been proposed. In these methods, the area of a device pattern, or the like, in a check window is calculated, and the shape of a dummy pattern to be placed in a remaining unoccupied region is determined based on the calculated area (for example, Japanese Unexamined Patent Publication No. 2001-237323).
However, in the above-described conventional methods, checking the pattern area ratio and/or the pattern occupancy ratio (hereinafter, “area ratio/occupancy ratio”) in a chip where a pattern and a dummy pattern are placed by a CAD (computer-aided design) system, or the like, is a prerequisite. That is, in the case where the area ratio/occupancy ratio cannot reach the target value even when any of various dummy patterns generated under a certain condition is placed, generation of dummy patterns under different conditions and placement of the generated dummy patterns, and accordingly verification of the area ratio/occupancy ratio, must be executed a plurality of times no matter which conventional method is employed. Therefore, layout correction has to be made after loop processing of the dummy pattern generation, and accordingly, an enormous length of time is required. As a result, the design efficiency is extremely low.
In any of the above-described conventional methods, verification of the pattern occupancy ratio in the check window is executed thoroughly. Thus, the process time increases as the degree of integration increases along with the advancement of miniaturization or as the area of one check window decreases (i.e., the number of check windows increases). That is, verification of the pattern occupancy ratio is possible only when no black box exists in a check window, in other words, only when all of the patterns are placed within a check window. Thus, the process time cannot be reduced by hierarchal processing, or the like.
In conventional methods wherein the area ratio/occupancy ratio is verified thoroughly after generation of dummy patterns, if the area ratio/occupancy ratio does not attain the target value (if the area ratio/occupancy ratio has not yet reached the target value), the number of retrogressive man-hours greatly increases, and accordingly, the design efficiency deteriorates significantly. In such conventional methods, dummy patterns are generated after the layout process is entirely completed. As a result, in some cases, the layout correction for attaining the target value of the area ratio/occupancy ratio is totally impossible.